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w78e58b 8 - bit microcontrolle r publication release date: march 18, 2002 - 1 - revision a3 1. general descripti on the w78e58b is an 8 - bit microcontroller which has an in - system programmable flash eprom for firmware updating. the instruction set of the w78e58b is fully compatible with the standard 8052. the w78e58b contains a 32k bytes of main ro m and a 4k bytes of auxiliary rom which allows the contents of the 32kb main rom to be updated by the loader program located at the 4kb auxiliary rom; 512 bytes of on - chip ram; four 8 - bit bi - directional and bit - addressable i/o ports; an additional 4 - bit po rt p4; three 16 - bit timer/counters; a serial port. these peripherals are supported by a eight sources two - level interrupt capability. to facilitate programming and verification, the rom inside the w78e58b allows the program memory to be programmed and read electronically. once the code is confirmed, the user can protect the code for security. the w78e58b microcontroller has two power reduction modes, idle mode and power - down mode, both of which are software selectable. the idle mode turns off the processor clock but allows for continued peripheral operation. the power - down mode stops the crystal oscillator for minimum power consumption. the external clock can be stopped at any time and in any state without affecting the processor. 2. features fully static design 8 - bit cmos microcontroller 32k bytes of in - system programmable flash eprom for application program (aprom) 4k bytes of auxiliary rom for loader program (ldrom) 512 bytes of on - chip ram (including 256 bytes of aux - ram, software selectable) 6 4k bytes program memory address space and 64k bytes data memory address space four 8 - bit bi - directional ports one 4 - bit multipurpose programmable port three 16 - bit timer/counters one full duplex serial port eight - sources, two - level interrupt capa bility built - in power management code protection packaged in - dip 40: w78e58b - 24/40 - plcc 44: w78e58bp - 24/40 - qfp 44: w78e58bf - 24/40
w78e58b - 2 - 3. p in configurations vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 39 40 34 35 36 37 38 30 31 32 33 26 27 28 29 21 22 23 24 25 p0.0, ad0 p0.1, ad1 p0.2, ad2 p0.3, ad3 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.5, a13 p2.6, a14 p2.7, a15 p2.0, a8 p2.1, a9 p2.2, a10 p2.3, a11 p2.4, a12 t2, p1.0 40-pin dip (w78e58b) p1.2 p1.3 p1.4 p1.5 p1.6 rxd, p3.0 txd, p3.1 p1.7 rst int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 wr, p3.6 rd, p3.7 xtal1 xtal2 vss t2ex, p1.1 44-pin plcc (w78e58bp) 44-pin qfp (w78e58bf) 40 2 1 44 43 42 41 6 5 4 3 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 10 9 8 7 14 13 12 11 16 15 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 a d 3 , p 0 . 3 t 2 , p 1 . 0 p 1 . 2 v d d a d 2 , p 0 . 2 a d 1 , p 0 . 1 a d 0 , p 0 . 0 t 2 e x , p 1 . 1 p 1 . 3 p 1 . 4 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 p4.1 p 4 . 0 int2, p4.3 / i n t 3 , p 4 . 2 34 40 39 38 37 36 35 44 43 42 41 33 32 31 30 29 28 27 26 25 24 23 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 22 21 20 19 18 17 16 15 14 13 12 11 4 3 2 1 8 7 6 5 10 9 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r a d 3 , p 0 . 3 t 2 , p 1 . 0 p 1 . 2 v d d a d 2 , p 0 . 2 a d 1 , p 0 . 1 a d 0 , p 0 . 0 t 2 e x , p 1 . 1 p 1 . 3 p 1 . 4 p 4 . 0 / i n t 3 , p 4 . 2 p4.1 int2, p4.3
w78e58b publication release date: march 18, 2002 - 3 - revision a3 4. pin description symbol type descriptions ea i external access enable: this pin forces the processor to execute the external rom. the rom address and data will not be presented on the bus if the ea pin is high. psen o h program store enable: psen enables the external rom data in the port 0 address/data bus. when internal rom access is performed, no psen strobe signal outputs originate from this pin. ale o h address latch enable: ale is used to enable the address latch that separa tes the address from the data on port 0. ale runs at 1/6th of the oscillator frequency. rst i l reset: a high on this pin for two machine cycles while the oscillator is running resets the device. xtal1 i crystal 1: this is the crystal oscillator input. this pin may be driven by an external clock. xtal2 o crystal 2: this is the crystal oscillator output. it is the inversion of xtal1. v ss i ground: ground potential. v dd i power supply: supply voltage for operation. p0.0 - p0.7 i/o d port 0: function i s the same as that of standard 8052. p1.0 - p1.7 i/o h port 1: function is the same as that of standard 8052. p2.0 - p2.7 i/o h port 2: port 2 is a bi - directional i/o port with internal pull - ups. this port also provides the upper address bits for accesse s to external memory. p3.0 - p3.7 i/o h port 3: function is the same as that of the standard 8052. p4.0 - p4.3 i/o h port 4: a bi - directional i/o. see details below. * note: type i: input, o: output, i/o: bi - directional, h: pull - high, l: pull - low, d: op en drain
w78e58b - 4 - 5. block diagram p3.0 p3.7 p1.0 p1.7 alu port 0 latch port 1 latch timer 1 timer 0 timer 2 port 1 uart xtal1 psen ale vss vcc rst xtal2 oscillator interrupt psw instruction decoder & sequencer reset block bus & clock controller sfr ram address power control 512 bytes ram & sfr stack pointer b addr. reg. incrementor pc dptr temp reg. t2 t1 acc port 3 latch port 4 latch port 3 port 2 latch p4.0 p4.3 port 4 port 0 port 2 p2.0 p2.7 p0.0 p0.7 32kb rom 4kb rom 6. functional descri ption the w78e58b architecture consists of a core controller surrounded by various registers, four general purpose i/o ports, one special purpose programmable 4 - bits i/o port, 512 bytes of ra m, three timer/counters, a serial port. the processor supports 111 different opcodes and references both a 64k program address space and a 64k data storage space. ram the internal data ram in the w78e58b is 512 bytes. it is divided into two banks: 256 byte s of scratchpad ram and 256 bytes of aux - ram. these rams are addressed by different ways. ram 0h - 7fh can be addressed directly and indirectly as the same as in 8051. address pointers are r0 and r1 of the selected register bank. ram 80h - ffh can onl y be addressed indirectly as the same as in 8051. address pointers are r0, r1 of the selected registers bank.
w78e58b publication release date: march 18, 2002 - 5 - revision a3 aux - ram 0h - ffh is addressed indirectly as the same way to access external data memory with the movx instruction. address pointer are r0 and r 1 of the selected register bank and dptr register. an access to external data memory locations higher than ffh will be performed with the movx instruction in the same way as in the 8051. the aux - ram is disable after a reset. setting the bit 4 in chpcon register will enable the access to aux - ram. when aux - ram is enabled the instructions of "movx @ri" will always access to on - chip aux - ram. when executing from internal program memory, an access to aux - ram will not affect the ports p0, p2, wr and rd . example, chpenr reg f6h chpcon reg bfh mov chpenr, #87h mov chpenr, #59h orl chpcon, #00010000b ; enable aux - ram mov chpenr, #00h mov r0, #12h mov a, #34h m ovx @r0, a ; write 34h data to 12h address. timers 0, 1 and 2 timers 0, 1, and 2 each consist of two 8 - bit data registers. these are called tl0 and th0 for timer 0, tl1 and th1 for timer 1, and tl2 and th2 for timer 2. the tcon and tmod registe rs provide control functions for timers 0, 1. the t2con register provides control functions for timer 2. rcap2h and rcap2l are used as reload/capture registers for timer 2. the operations of timer 0 and timer 1 are the same as in the w78c51. timer 2 is a 1 6 - bit timer/counter that is configured and controlled by the t2con register. like timers 0 and 1, timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit c/t2 in t2con. timer 2 has three operating mo des: capture, auto - reload, and baud rate generator. the clock speed at capture or auto - reload mode is the same as that of timers 0 and 1. clock the w78e58b is designed with either a crystal oscillator or an external clock. internally, the clock is divided by two before it is used by default. this makes the w78e58b relatively insensitive to duty cycle variations in the clock. crystal oscillator the w78e58b incorporates a built - in crystal oscillator. to make the oscillator work, a crystal must be connected ac ross pins xtal1 and xtal2. in addition, a load capacitor must be connected from each pin to ground. external clock an external clock should be connected to pin xtal1. pin xtal2 should be left unconnected. the xtal1 input is a cmos - type input, as required b y the crystal oscillator.
w78e58b - 6 - power management idle mode setting the idl bit in the pcon register enters the idle mode. in the idle mode, the internal clock to the processor is stopped. the peripherals and the interrupt logic continue to be clocked. the proce ssor will exit idle mode when either an interrupt or a reset occurs. power - down mode when the pd bit in the pcon register is set, the processor enters the power - down mode. in this mode all of the clocks are stopped, including the oscillator. to exit from p ower - down mode is by a hardware reset or external interrupts int0 to int1 when enabled and set to level triggered. reduce emi emission the w78e58b allows user to diminish the gain of on - chip oscillator amplifier by using programme r to clear the b7 bit of security register. once b7 is set to 0, a half of gain will be decreased. care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the external crystal operating improperl y at high frequency. the value of c1 and c2 may need some adjustment while running at lower gain. reset the external reset signal is sampled at s5p2. to take effect, it must be held high for at least two machine cycles while the oscillator is run ning. an internal trigger circuit in the reset line is used to deglitch the reset line when the w78e58b is used with an external rc network. the reset logic also has a special glitch removal circuit that ignores glitches on the reset line. during reset, th e ports are initialized to ffh, the stack pointer to 07h, pcon (with the exception of bit 4) to 00h, and all of the other sfr registers except sbuf to 00h. sbuf is not reset. w78e58b special function registers (sfrs) and reset values f8 ff f0 +b 00000000 chpenr 00000000 f7 e8 ef e0 +acc 00000000 e7 d8 +p4 xxxx1111 df d0 +psw 00000000 d7 c8 +t2con 00000000 rcap2l 00000000 rcap2h 00000000 tl2 00000000 th2 00000000 cf c0 xicon 00000000 p4cona 00000000 p4c onb 00000000 sfral 00000000 sfrah 00000000 sfrfd 00000000 sfrcn 00000000 c7 b8 +ip 00000000 chpcon 0xx00000 bf b0 +p3 00000000 p43al 00000000 p43ah 00000000 b7
w78e58b publication release date: march 18, 2002 - 7 - revision a3 continued a8 +ie 00000000 p42al 00000000 p42ah 00000000 p2econ 0000xx00 af a 0 +p2 11111111 a7 98 +scon 00000000 sbuf xxxxxxxx 9f 90 +p1 11111111 p41al 00000000 p41ah 00000000 97 88 +tcon 00000000 tmod 00000000 tl0 00000000 tl1 00000000 th0 00000000 th1 00000000 8f 80 +p0 11111111 sp 00000111 dpl 00000000 dph 00000000 p40al 00000000 p40ah 00000000 pcon 00110000 87 notes: 1.the sfrs marked with a plus sign(+) are both byte - and bit - addressable. 2. the text of sfr with bold type characters are extension function registers. port 4 port 4, address d8h, is a 4 - bit multipurpose programmable i/o port. each bit can be configured individually by software. the port 4 has four different operation modes. mode 0: p4.0 - p4.3 is a bi - directional i/o port which is same as port 1. p4.2 and p4.3 also serve as external i nterrupt int3 and nt2 i if enabled. mode 1: p4.0 - p4.3 are read strobe signals that are synchronized with rd signal at specified addresses. these signals can be used as chip - select signals for external peripheral s. mode 2: p4.0 - p4.3 are write strobe signals that are synchronized with wr signal at specified addresses. these signals can be used as chip - select signals for external peripherals. mode 3: p4.0 - p4.3 are read/write strobe signals that are synchronized with rd or wr signal at specified addresses. these signals can be used as chip - select signals for external peripherals. when port 4 is configured with the feature of chip - select signals, the chip - select sig nal address range depends on the contents of the sfr p4xah, p4xal, p4cona and p4conb. the registers p4xah and p4xal contain the 16 - bit base address of p4.x. the registers p4cona and p4conb contain the control bits to configure the port 4 operation mode. int2 / nt3 i two additional external interrupts, int2 and int3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80c52. the functions/status of these interrupts are determined /shown by the bits in the xicon (external interrupt control) register. the xicon register is bit - addressable but is not a standard register in the standard 80c52. its address is at 0c0h. to set/clear bits in the xicon register, one can use the "setb ( clr ) bit" instruction. for example, "setb 0c2h" sets the ex2 bit of xicon.
w78e58b - 8 - xicon - external interrupt control (c0h) px3 ex3 ie3 it3 px2 ex2 ie2 it2 px3: external interrupt 3 priority high if set ex3: external interrupt 3 enable if set ie3: if i t3 = 1, ie3 is set/cleared automatically by hardware when interrupt is detected/serviced it3: external interrupt 3 is falling - edge/low - level triggered when this bit is set/cleared by software px2: external interrupt 2 priority high if set ex2: external int errupt 2 enable if set ie2: if it2 = 1, ie2 is set/cleared automatically by hardware when interrupt is detected/serviced it2: external interrupt 2 is falling - edge/low - level triggered when this bit is set/cleared by software eight - source interrupt informati on interrupt source vector address polling sequence within priority level enable required settings interrupt type edge/level external interrupt 0 03h 0 (highest) ie.0 tcon.0 timer/counter 0 0bh 1 ie.1 - external interrupt 1 13h 2 ie.2 tcon.2 timer/coun ter 1 1bh 3 ie.3 - serial port 23h 4 ie.4 - timer/counter 2 2bh 5 ie.5 - external interrupt 2 33h 6 xicon.2 xicon.0 external interrupt 3 3bh 7 (lowest) xicon.6 xicon.3 p4conb (c3h) bit name function 7, 6 p43fun1 p43fun0 00: mode 0. p4.3 is a general purpose i/o port which is the same as port1. 01: mode 1. p4.3 is a read strobe signal for chip select purpose. the address range depends on the sfr p43ah, p43al, p43cmp1 and p43cmp0. 10: mode 2. p4.3 is a write strobe signal for chip select purpose. the a ddress range depends on the sfr p43ah, p43al, p43cmp1 and p43cmp0. 11: mode 3. p4.3 is a read/write strobe signal for chip select purpose. the address range depends on the sfr p43ah, p43al, p43cmp1, and p43cmp0.
w78e58b publication release date: march 18, 2002 - 9 - revision a3 p4conb (c3h), continued bit name funct ion 5, 4 p43cmp1 p43cmp0 chip - select signals address comparison: 00: compare the full address (16 bits length) with the base address register p43ah, p43al. 01: compare the 15 high bits (a15 - a1) of address bus with the base address register p43ah, p43a l. 10: compare the 14 high bits (a15 - a2) of address bus with the base address register p43ah, p43al. 11: compare the 8 high bits (a15 - a8) of address bus with the base address register p43ah, p43al. 3, 2 p42fun1 p42fun0 the p4.2 function contr ol bits which are the similar definition as p43fun1, p43fun0. 1, 0 p42cmp1 p42cmp0 the p4.2 address comparator length control bits which are the similar definition as p43cmp1, p43cmp0. p4cona (c2h) bit name function 7, 6 p41fun1 p41fun0 the p4.1 functi on control bits which are the similar definition as p43fun1, p43fun0. 5, 4 p41cmp1 p41cmp0 the p4.1 address comparator length control bits which are the similar definition as p43cmp1, p43cmp0. 3, 2 p40fun1 p40fun0 the p4.0 function control bits which ar e the similar definition as p43fun1, p43fun0. 1, 0 p40cmp1 p40cmp0 the p4.0 address comparator length control bits which are the similar definition as p43cmp1, p43cmp0. p2econ (aeh) bit name function 7 p43csinv the active polarity of p4.3 when pin p4.3 is defined as read and/or write strobe signal. 1: p4.3 is active high when pin p4.3 is defined as read and/or write strobe signal. 0: p4.3 is active low when pin p4.3 is defined as read and/or write strobe signal. 6 p42csinv the similarity definition as p43sinv. 5 p41csinv the similarity definition as p43sinv. 4 p40csinv the similarity definition as p43sinv. 3 - reserve 2 - reserve 1 - 0 0 - 0
w78e58b - 10 - port 4 base address registers p40ah, p40al the base address register for comparator of p4.0. p40ah contain s the high - order byte of address, p40al contains the low - order byte of address. p41ah, p41al the base address register for comparator of p4.1. p41ah contains the high - order byte of address, p41al contains the low - order byte of address. p42ah, p42al the bas e address register for comparator of p4.2. p42ah contains the high - order byte of address, p42al contains the low - order byte of address. p43ah, p43al the base address register for comparator of p4.3. p43ah contains the high - order byte of address, p43al cont ains the low - order byte of address. p4 (d8h) bit name function 7 - reserve 6 - reserve 5 - reserve 4 - reserve 3 p43 port 4 data bit which outputs to pin p4.3 at mode 0. 2 p42 port 4 data bit. which outputs to pin p4.2 at mode 0. 1 p41 port 4 data b it. which outputs to pin p4.1at mode 0. 0 p40 port 4 data bit which outputs to pin p4.0 at mode 0. here is an example to program the p4.0 as a write strobe signal at the i/o port address 1234h - 1237h and positive polarity, and p4.1 - p4.3 are used as ge neral i/o ports. mov p40ah, #12h mov p40al, #34h ; base i/o address 1234h for p4.0 mov p4cona, #00001010b ; p4.0 a write strobe signal and address line a0 and a1 are masked. mov p4conb, #00h ; p4.1 - p4.3 as general i/o port which are the same as port1 mov p2econ, #10h ; write the p40sinv = 1 to inverse the p4.0 write strobe polarity ; default is negative. then any instruction movx @dptr, a (with dptr = 1234h - 1237h) will generate the positive polarity write strobe signal at pin p4.0. and the instruc tion mov p4, #xx will output the bit3 to bit1 of data #xx to pin p4.3 - p4.1.
w78e58b publication release date: march 18, 2002 - 11 - revision a3 address bus bit length selectable comparator register p4xal p4xah equal p4.x mux 4->1 p4 register p4.x read write data i/o rd_cs wr_cs rd/wr_cs p4xcmp0 p4xcmp1 p4xfun0 p4xfun1 p4xcsinv p4.x input data bus register pin in - system programming (isp) mode the w78e58b equips one 32k byte of main rom bank for application program (called aprom) and one 4k byte of auxiliary rom bank f or loader program (called ldrom). in the normal operation, the microcontroller executes the code in the aprom. if the content of aprom needs to be modified, the w78e58b allows user to activate the in - system programming (isp) mode by setting the chpcon regi ster. the chpcon is read - only by default, software must write two specific values 87h, then 59h sequentially to the chpenr register to enable the chpcon write attribute. writing chpenr register with the values except 87h and 59h will close chpcon register write attribute. the w78e58b achieves all in - system programming operations including enter/exit isp mode, program, erase, read ... etc, during device in the idle mode. setting the bit chpcon.0 the device will enter in - system programming mode after a wake - u p from idle mode. because device needs proper time to complete the isp operations before awaken from idle mode, software may use timer interrupt to control the duration for device wake - up from idle mode. to perform isp operation for revising contents of ap rom, software located at aprom setting the chpcon register then enter idle mode, after awaken from idle mode the device executes the corresponding interrupt service routine in ldrom. because the device will clear the program counter while switching from ap rom to ldrom, the first execution of reti instruction in interrupt service routine will jump to 00h at ldrom area. the device offers a software reset for switching back to aprom while the content of aprom has been updated completely. setting chpcon registe r bit 0, 1 and 7 to logic - 1 will result a software reset to reset the cpu . the software reset serves as a external reset. this in - system programming feature makes the job easy and efficient in which the application needs to update firmware frequently. in s ome applications, the in - system programming feature make it possible to easily update the system firmware without opening the chassis.
w78e58b - 12 - sfrah, sfral: the objective address of on - chip rom in the in - system programming mode. sfrah contains the high - order byt e of address, sfral contains the low - order byte of address. sfrfd: the programming data for on - chip rom in programming mode. sfrcn: the control byte of on - chip rom programming mode. sfrcn (c7) bit name function 7 - reserve. 6 wfwin on - chip rom bank selec t for in - system programming. 0: 32k bytes rom bank is selected as destination for re - programming. 1: 4k bytes rom bank is selected as destination for re - programming. 5 oen rom output enable. 4 cen rom chip enable. 3, 2, 1, 0 ctrl [3:0] the flash co ntrol signals mode wfwin ctrl<3:0> oen cen sfrah, sfral sfrfd erase 32kb aprom 0 0010 1 0 x x program 32kb aprom 0 0001 1 0 address in data in read 32kb aprom 0 0000 0 0 address in data out erase 4kb ldrom 1 0010 1 0 x x program 4kb ldrom 1 0001 1 0 address in data in read 4kb ldrom 1 0000 0 0 address in data out
w78e58b publication release date: march 18, 2002 - 13 - revision a3 in - system programming control register (chpcon) chpcon (bfh) bit name function 7 swreset (f04kmode) when this bit is set to 1, and both fbootsl and fprogen are set to 1. it will enfor ce microcontroller reset to initial condition just like power on reset. this action will re - boot the microcontroller and start to normal operation. to read this bit in logic - 1 can determine that the f04kboot mode is running. 6 - reserve. 5 - reserve. 4 enauxram 1: enable on - chip aux - ram. 0: disable the on - chip aux - ram 3 0 must set to 0. 2 0 must set to 0. 1 fbootsl the program location select. 0: the loader program locates at the 32 kb aprom. 4kb ldrom is destination for re - program ming. 1: the loader program locates at the 4 kb memory bank. 32kb aprom is destination for re - programming. 0 fprogen rom programming enable. 1: enable. the microcontroller enter the in - system programming mode after entering the idle mode and wake - up fr om interrupt. during in - system programming mode, the operation of erase, program and read are achieve when device enters idle mode. 0: disable. the on - chip flash memory is read - only. in - system programmability is disabled. f04kboot mode (boot from ldrom) by default, the w78e58b boots from aprom program after a power on reset. on some occasions, user can force the w78e58b to boot from the ldrom program via following settings . the possible situation that you need to enter f04kboot mode when the aprom progra m can not run properly and device can not jump back to ldrom to execute in - system programming function. then you can use this f04kboot mode to force the w78e58b jumps to ldrom and executes in - system programming procedure. when you design your system, you m ay reserve the pins p2.6, p2.7 to switches or jumpers. for example in a cd - rom system, you can connect the p2.6 and p2.7 to play and eject buttons on the panel. when the aprom program fails to execute the normal application program. user can press both two buttons at the same time and then turn on the power of the personal computer to force the w78e58b to enter the f04kboot mode. after power on of personal computer, you can release both buttons and finish the in - system programming procedure to update the ap rom code. in application system design, user must take care of the p2, p3, ale, ea and psen pin value at reset to prevent from accidentally activating the programming mode or f04kboot mode.
w78e58b - 14 - f04kboot mode p4.3 p2.7 p2.6 mode x l l fo4kboot l x x fo4kboot p2.7 p2.6 rst 30 ms hi-z the reset timing for entering f04kboot mode 10 ms hi-z
w78e58b publication release date: march 18, 2002 - 15 - revision a3 start the algorithm of in-system programming enter in-system programming mode ? (conditions depend on user's application) setting control registers mov chpenr,#87h mov chpenr,#59h mov chpcon,#03h setting timer (about 1.5 us) and enable timer interrupt start timer and enter idle mode. (cpu will be wakened from idle mode by timer interrupt, then enter in-system programming mode) execute the normal application program no yes end cpu will be wakened by interrupt and re-boot from 4kb ldrom to execute the loader program. go part 1:32kb aprom procedure of entering in-system programming mode
w78e58b - 16 - part 2: 4kb ldrom procedure of updating the 32kb aprom go timer interrupt service routine: stop timer & disable interrupt is f04kboot mode? (chpcon.7=1) reset the chpcon register: mov chpenr,#87h mov chpenr,#59h mov chpcon,#03h no yes setting timer and enable timer interrupt for wake-up . (15 ms for erasing operation) setting erase operation mode: mov sfrcn,#22h (erase 32kb aprom) start timer and enter idle mode. (erasing...) end of erase operation. cpu will be wakened by timer interrupt. pgm pgm setting timer and enable timer interrupt for wake-up . (50us for program operation) end of programming ? get the parameters of new code (address and data bytes) through i/o ports, uart or other interfaces. is currently in the f04kboot mode ? setting control registers for programming: mov sfrah,#address_h mov sfral,#address_l mov sfrfd,#data mov sfrcn,#21h software reset cpu and re-boot from the 32kb aprom. mov chpenr,#87h mov chpenr,#59h mov chpcon,#83h end executing new code from address 00h in the 32kb aprom. hardware reset to re-boot from new 32 kb aprom. (s/w reset is invalid in f04kboot mode) yes no yes no
w78e58b publication release date: march 18, 2002 - 17 - revision a3 7. security during the on - chip rom programming mode, the rom can be programmed and verified repeatedly. until the code inside the rom is confirmed ok, the code can be protected. the protection of rom and those operations on it are described below. the w78e58b has a security register that can be accessed in programming mode. those bits of the security registers can not be changed once they have been programmed from high to low. they can only be reset through erase - all operation. the security register is located at the 0ffffh of the ldrom space. b0 b1 b0: lock bit, logic 0: active b1: movc inhibit, logic 0: the movc instruction in external memory cannot access the code in internal memory. logic 1: no restriction. default 1 for all security bits. special setting register security bits 4kb on-chip rom program memory reserved security register ffffh 0000h 0fffh reserved b2 b2: encryption logic 0: the encryption logic enable logic 1: the encryption logic disable reserved bits must be kept in logic 1. b7 b07: osillator control logic 0: 1/2 gain logic 1: full gain ldrom reserved 32kb on-chip rom program memory aprom 7fffh lock bit this bit is used to protect the customer's program code in the w78e58b. it may be set after the progr ammer finishes the programming and verifies sequence. once this bit is set to logic 0, both the rom data and security register can not be accessed again. movc inhibit this bit is used to restrict the accessible region of the movc instruction. it can preven t the movc instruction in external program memory from reading the internal program code. when this bit is set to logic 0, a movc instruction in external program memory space will be able to access code only in the external memory, not in the internal memo ry. a movc instruction in internal program memory space will always be able to access the rom data in both internal and external memory. if this bit is logic 1, there are no restrictions on the movc instruction. encryption this bit is used to enable/disabl e the encryption logic for code protection. once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. only whole chip erase will reset this bit.
w78e58b - 18 - oscillator control w78e58b/e516 allow user to diminish the gain o f on - chip oscillator amplifier by using programmer to set the bit b7 of security register. once b7 is set to 0, a half of gain will be decreased. care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may improperly affect the external crystal operation at high frequency above 24 mhz. the value of r and c1, c2 may need some adjustment while running at lower gain. 8. absolute maximum ratings parameter symbol min. max. unit dc power supply v dd - v ss - 0.3 +6 .0 v input voltage v in v ss - 0.3 v dd +0.3 v operating temperature t a 0 70 c storage temperature t st - 55 +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the devic e. 9. dc characteristic s (v dd - v ss = 5v 10%, t a = 25 c, fosc = 20 mhz, unless otherwise specified.) parameter sym. specification test conditions min. max. unit operating voltage v dd 4.5 5.5 v rst = 1, p0 = v dd operating current i dd - 20 ma no load v dd = 5.5v idle current i idle - 6 ma idle mode v dd = 5.5v power down current i pwdn - 50 m a power - down mode v dd = 5.5v input current p1, p2, p3, p4 i in1 - 50 +10 m a v dd = 5.5v v in = 0v or v dd input current rst i in2 - 10 +300 m a v dd = 5.5v 0v < v in < v dd i nput leakage current p0, ea i lk - 10 +10 m a v dd = 5.5v 0v < v in < v dd logic 1 to 0 transition current p1, p2, p3, p4 i tl [*4] - 500 - m a v dd = 5.5v v in = 2.0v
w78e58b publication release date: march 18, 2002 - 19 - revision a3 dc characteristics, continued parameter sym. specification test conditions min. max. unit input low voltage p0, p1, p2, p3, p4, ea v il1 0 0.8 v v dd = 4.5v input low voltage rst v il2 0 0.8 v v dd = 4.5v input low voltage xtal1 [*4] v il3 0 0.8 v v dd = 4.5v input high voltage p0, p1, p2, p3, p4, ea v ih1 2.4 v dd +0.2 v v dd = 5.5v input high voltage rst v ih2 3.5 v dd +0.2 v v dd = 5.5v input high voltage xtal1 [*4] v ih3 3.5 v dd +0.2 v v dd = 5.5v output low voltage p1, p2, p3, p4 v ol1 - 0.45 v v dd = 4.5v i ol = +2 ma output low voltage p0 , ale, psen [*3] v ol2 - 0.45 v v dd = 4.5v i ol = +4 ma sink current p1, p3, p4 isk1 4 12 ma v dd = 4.5v v in = 0.45v sink current p0, p2, ale, psen isk2 10 20 ma v dd = 4.5v v in = 0.45v output high voltage p1, p2, p3, p4 v oh1 2.4 - v v dd = 4.5v i oh = - 100 m a output high voltage p0, ale, psen [*3] v oh2 2.4 - v v dd = 4.5v i oh = - 400 m a source current p1, p2, p3, p4 isr1 - 120 - 250 m a v dd = 4.5v v in = 2.4v source current p0, p2, ale, psen isr2 - 8 - 20 ma v dd = 4.5v v in = 2.4v notes: *1. rst pin is a schmitt trigger input. *2. p0, ale and psen are tested in the external access mode. *3. xtal1 is a cmos input. *4. pins of p1, p2, p3, p4 can source a transition current when th ey are being externally driven from 1 to 0.
w78e58b - 20 - 10. ac characteristics the ac specifications are a function of the particular process used to manufacture the part, the ratings of the i/o buffers, the capacitive load, and the internal routing capacitance. mos t of the specifications can be expressed in terms of multiple input clock periods (t cp ), and actual parts will usually experience less than a 20 ns variation. the numbers below represent the performance expected from a 0.6 micron cmos process when using 2 and 4 ma output buffers. clock input waveform t t xtal1 f ch cl op, t cp parameter symbol min. typ. max. unit notes operating speed f op 0 - 40 mhz 1 clock period t cp 25 - - ns 2 clock high t ch 10 - - ns 3 clock low t cl 10 - - ns 3 notes: 1. the clock may be stopped indefinitely in either state. 2. the t cp specification is used as a reference in other specifications. 3. there are no duty cycle requirements on the xtal1 input. program fetch cycle parameter symbol min. typ. max. unit notes add ress valid to ale low t aas 1 t cp - d - - ns 4 address hold from ale low t aah 1 t cp - d - - ns 1, 4 ale low to psen low t apl 1 t cp - d - - ns 4 psen low to data valid t pda - - 2 t cp ns 2 data hold after psen high t pdh 0 - 1 t cp ns 3 data float after psen high t pdz 0 - 1 t cp ns ale pulse width t alw 2 t cp - d 2 t cp - ns 4 psen pulse width t psw 3 t cp - d 3 t cp - ns 4 notes: 1. p0.0 - p0.7, p2.0 - p2.7 remain stable throughout entire memory cycle. 2. memory access time is 3 t cp . 3. data have been latched internal ly prior to psen going high. 4. " d " (due to buffer driving delay and wire loading) is 20 ns.
w78e58b publication release date: march 18, 2002 - 21 - revision a3 data read cycle parameter symbol min. typ. max. unit notes ale low to rd low t dar 3 t cp - d - 3 t cp+ d ns 1, 2 rd low to data valid t dda - - 4 t cp ns 1 data hold from rd high t ddh 0 - 2 t cp ns data float from rd high t ddz 0 - 2 t cp ns rd pulse width t drd 6 t cp - d 6 t cp - ns 2 notes: 1. data memory access time is 8 t cp . 2. " d " (due to buffer driving delay and wire loading) is 20 ns. data write cycle para meter symbol min. typ. max. unit ale low to wr low t daw 3 t cp - d - 3 t cp + d ns data valid to wr low t dad 1 t cp - d - - ns data hold from wr high t dwd 1 t cp - d - - ns wr pulse width t dwr 6 t cp - d 6 t cp - ns note: " d " (due to buffer driving delay and wire loadi ng) is 20 ns. port access cycle parameter symbol min. typ. max. unit port input setup to ale low t pds 1 tcp - - ns port input hold from ale low t pdh 0 - - ns port output to ale t pda 1 tcp - - ns note: ports are read during s5p2, and output data become s available at the end of s6p2. the timing data are referenced to ale, since it provides a convenient reference.
w78e58b - 22 - 11. timing waveforms program fetch cycle s1 xtal1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale port 2 a0-a7 a0-a7 data a0-a7 code t a0-a7 data code port 0 psen pdh, t pdz t pda t aah t aas t psw t apl t alw data read cycle s2 s3 s5 s6 s1 s2 s3 s4 s5 s6 s1 s4 xtal1 ale psen data a8-a15 port 2 port 0 a0-a7 rd t ddh, t ddz t dda t drd t dar
w78e58b publication release date: march 18, 2002 - 23 - revision a3 timing waveforms, continued data write cyc le s2 s3 s5 s6 s1 s2 s3 s4 s1 s5 s6 s4 xtal1 ale psen a8-a15 data out port 2 port 0 a0-a7 wr t t daw dad t dwr t dwd port access cycle xtal1 ale s5 s6 s1 data out t t port input t sample pda pdh pds
w78e58b - 24 - 12. typical application circuits expanded external program memory and crystal ad0 a0 a0 a0 10 a1 9 a2 8 a3 7 a4 6 a5 5 a6 4 a7 3 a8 25 a9 24 a10 21 a11 23 a12 2 a13 26 a14 27 a15 1 ce 20 oe 22 o0 11 o1 12 o2 13 o3 15 o4 16 o5 17 o6 18 o7 19 27512 ad0 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74ls373 ad0 ea 31 xtal1 19 xtal2 18 rst 9 int0 12 int1 13 t0 14 t1 15 p1.0 1 p1.1 2 p1.2 3 p1.3 4 p1.4 5 p1.5 6 p1.6 7 p1.7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 wr p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd 16 psen 29 ale 30 txd 11 rxd 10 w78e58b 10 u 8.2 k v crystal c1 c2 r ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd a1 a2 a3 a4 a5 a6 a7 a1 a2 a3 a4 a5 a6 a7 a8 a9 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a10 a11 a12 a13 a14 a15 gnd a9 a10 a11 a12 a13 a14 a15 dd figure a crystal c1 c2 r 6 mhz 47p 47p - 16 mhz 30p 30p - 24 mhz 15p 10p - 40mhz 5p 5p 6.8k above table shows the reference values for crystal applications. notes: 1. c1, c2, r components refer to figure a 2. crystal layout must get close to xtal1 and xtal2 pins on user's application board.
w78e58b publication release date: march 18, 2002 - 25 - revision a3 typical application circuit, continued e xpanded external d ata memory and oscillator 10 u 8.2 k oscillator ea 31 xtal1 19 xtal2 18 rst 9 int0 12 int1 13 t0 14 t1 15 p1.0 1 p1.1 2 p1.2 3 p1.3 4 p1.4 5 p1.5 6 p1.6 7 p1.7 8 p0.0 39 p0.1 38 p0.2 37 p0.3 36 p0.4 35 p0.5 34 p0.6 33 p0.7 32 p2.0 21 p2.1 22 p2.2 23 p2.3 24 p2.4 25 p2.5 26 p2.6 27 p2.7 28 rd 17 wr 16 psen 29 ale 30 txd 11 rxd 10 w78e58b ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a0 a1 a2 a3 a4 a5 a6 a7 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74ls373 a0 a1 a2 a3 a4 a5 a6 a7 10 9 8 7 6 5 4 3 a0 a1 a2 a3 a4 a5 a6 a7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 11 12 13 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 a8 a9 a10 a11 a12 a13 a14 25 24 21 23 26 1 20 2 a8 a9 a10 a11 a12 a13 a14 ce gnd a8 a9 a10 a11 a12 a13 a14 gnd 22 27 oe wr 20256 v dd v dd figure b 13. package dimensio ns 40 - pin dip seating plane 1. dimension d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimension d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. . 1.372 1.219 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm 0.050 1.27 0.210 5.334 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.406 0.254 3.937 0.457 4.064 0.559 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.203 3.048 0.254 3.302 0.356 3.556 0.540 0.550 0.545 13.72 13.97 13.84 17.01 15.24 14.986 15.494 0.600 0.590 0.610 2.286 2.54 2.794 0.090 0.100 0.110 a b c d e a l s a a 1 2 e b 1 1 e e 1 a 2.055 2.070 52.20 52.58 0 15 0.090 2.286 0.650 0.630 16.00 16.51 protrusion/intrusion. 4. dimension b1 does not include dambar 5. controlling dimension: inches. 15 0 e a a a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1 2
w78e58b - 26 - package dimensions, continued 44 - pin plcc 44 40 39 29 28 18 17 7 6 1 l c 1 b 2 a h d d e b e h e y a a 1 seating plane d g g e symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h e l y a a 1 2 e b 1 h d g g d e notes: on final visual inspection spec. 4. general appearance spec. should be based 3. controlling dimension: inches protrusion/intrusion. 2. dimension b1 does not include dambar flash. 1. dimension d & e do not include interlead 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.508 3.683 0.66 0.406 0.203 16.46 14.99 17.27 2.296 3.81 0.711 0.457 0.254 16.59 15.49 17.53 2.54 1.27 4.699 3.937 0.813 0.559 0.356 16.71 16.00 17.78 2.794 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680 q 44 - pin pqfp seating plane 11 22 12 see detail f e b a y 1 a a l l 1 c e e h 1 d 44 h d 34 33 detail f 1. dimension d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeter 4. general appearance spec. should be based on final visual inspection spec. 0.254 0.101 0.010 0.004 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.006 0.152 --- 0.002 0.075 0.01 0.081 0.014 0.087 0.018 1.90 0.25 0.05 2.05 0.35 2.20 0.45 0.390 0.025 0.063 0.003 0 7 0.394 0.031 0.398 0.037 9.9 0.80 0.65 1.6 10.00 0.8 10.1 0.95 0.398 0.394 0.390 0.530 0.520 0.510 13.45 13.2 12.95 10.1 10.00 9.9 7 0 0.08 0.031 0.01 0.02 0.25 0.5 --- --- --- --- --- q 2 q 0.025 0.036 0.635 0.952 0.530 0.520 0.510 13.45 13.2 12.95 0.051 0.075 1.295 1.905
w78e58b publication release date: march 18, 2002 - 27 - revision a3 14. application notes in - system programming software examples this application note illustrates the in - system programmability of the winbond w78e58b rom microcontroller. in this example, microcontroller will boot from 32kb aprom bank and waiting f or a key to enter in - system programming mode for re - programming the contents of 32kb aprom. while entering in - system programming mode, microcontroller executes the loader program in 4kb ldrom bank. the loader program erases the 32kb aprom then reads the ne w code data from external sram buffer (or through other interfaces) to update the 32kb aprom. example 1: ;******************************************************************************************************************* ;* example of 32k aprom program : program will scan the p1.0. if p1.0 = 0, enters in - system ;* programming mode for updating the content of aprom code else executes the current rom code. ;* xtal = 16 mhz ;********************************************************************************* ********************************** .chip 8052 .ramchk off .symbols chpcon equ bfh chpenr equ f6h sfral equ c4h sfrah equ c5h sfrfd equ c6h sfrcn equ c7h org 0h ljmp 100h ; jump to main program ;********** ************************************************************** ;* timer0 service vector org = 000bh ;************************************************************************ org 00bh clr tr0 ; tr0 = 0, stop tim er0 mov tl0, r6 mov th0, r7 reti ;************************************************************************ ;* 32k aprom main program ;************************************************************************ or g 100h main_32k: mov a, p1 ; scan p1.0 anl a, #01h cjne a, #01h, program_32k ; if p1.0 = 0, enter in - system programming mode jmp normal_mode program_32k: mov chpenr, #87h ; chpenr = 87h, chpcon registe r wrte enable mov chpenr, #59h ; chpenr = 59h, chpcon register write enable mov chpcon, #03h ; chpcon = 03h, enter in - system programming mode
w78e58b - 28 - mov tcon, #00h ; tr = 0 timer0 stop mov ip, #00h ; ip = 00h mov ie, #82h ; timer0 interrupt enable for wake - up from idle mode mov r6, #f0h ; tl0 = f0h mov r7, #ffh ; th0 = ffh mov tl0, r6 mov th0, r7 mov tmod, #01h ; tmod = 01h, set timer0 a 16 - bit timer mov tcon, #10h ; tcon = 10h, tr0 = 1, go mov pcon, #01h ; enter idle mode for launching the in - system ; programming ;**************************************************************** **************** ;* normal mode 32kb aprom program: depending user's application ;******************************************************************************** normal_mode: . ; user's application program . . . example 2: ;** **************************************************************************************************************************** example of 4 kb ldrom program: this loader program will erase the 32kb aprom first, then reads the new ;* code from external sram a nd program them into 32 kb aprom bank. xtal = 16 mhz ;***************************************************************************************************************************** .chip 8052 .ramchk off .symbols chpcon equ bfh chpenr equ f6h sfral equ c4h sfrah equ c5h sfrfd equ c6h sfrcn equ c7h org 000h ljmp 100h ; jump to main program ;************************************************************************ ;* 1. timer0 service vector org = 0bh ;************************************************************************ org 000bh clr tr0 ; tr0 = 0, stop timer0 mov tl0, r6 mov th0, r7 reti ;***************************************************** ******************* ;* 4kb ldrom main program ;************************************************************************ org 100h
w78e58b publication release date: march 18, 2002 - 29 - revision a3 main_4k: mov sp, #c0h mov chpenr, #87h ; chpenr = 87h, chpcon write enable. mov chpenr, #59h ; chpenr = 59h, chpcon write enable. mov a, chpcon anl a, #80h cjne a, #80h, update_32k ; check f04kboot mode ? mov chpcon, #03h ; chpcon = 03h, enable in - system programming. mov chpenr, #00h ; disa ble chpcon write attribute mov tcon, #00h ; tcon = 00h, tr = 0 timer0 stop mov tmod, #01h ; tmod = 01h, set timer0 a 16bit timer mov ip, #00h ; ip = 00h mov ie, #82h ; ie = 82h, timer0 interrupt enabled mov r6, #f0h mov r7, #ffh mov tl0, r6 mov th0, r7 mov tcon, #10h ; tcon = 10h, tr0 = 1, go mov pcon, #01h ; enter idle mode update_32k: mov chpenr, #00h ; disable chpcon write - attribute mov tcon, #00h ; tcon = 00h , tr = 0 tim0 stop mov ip, #00h ; ip = 00h mov ie, #82h ; ie = 82h, timer0 interrupt enabled mov tmod, #01h ; tmod = 01h, mode1 mov r6, #e0h ; set wake - up time for erase op eration, about 15 ms. depending ; on user's system clock rate. mov r7, #b1h mov tl0, r6 mov th0, r7 erase_p_4k: mov sfrcn, #22h ; sfrcn(c7h) = 22h erase 32k mov tcon, #10h ; tcon = 10h, tr0 = 1,go mov pcon, #01h ; enter idle mode (for erase operation) ;********************************************************************* ;* blank check ;********************************************************************* mov sfrcn, #0 h ; read 32kb aprom mode mov sfrah, #0h ; start address = 0h mov sfral, #0h mov r6, #feh ; set timer for read operation, about 1.5 m s. mov r7, #ffh mov tl0, r6 mov th0, r7 blank_check_loop: setb tr0 ; enable timer 0 mov pcon, #01h ; enter idle mode mov a, sfrfd ; re ad one byte cjne a, #ffh, blank_ check_error
w78e58b - 30 - inc sfral ; nex t address mov a, sfral jnz blank_check_loop inc sfrah mov a, sfrah cjne a, #80h, blank_ c heck_loop ; end ad dress = 7fffh jmp program_32krom blank_check_error: mov p1, #f0h mov p3, #f0h jmp $ ;******************************************************************************* ;* re - programming 32kb aprom bank ;** ***************************************************************************** program_32krom: mov dptr, #0h ; the address of new rom code mov r2, # 00h ; target low byte address mov r1, #00h ; target high byte address mov dptr, #0h ; external sram buffer address mov sfrah, r1 ; sfrah, targe t high address mov sfrcn , #21h ; sfrcn(c7 h) = 21 (program 32k ) mov r6, #beh ; set timer for programming, abo ut 50 m s. mov r7, #ffh mov tl0, r6 mov th0, r7 prog_d_32k: mov sfral, r2 ; sfral(c4h) = low byte address movx a, @dptr ; read data from external sram buffer . by according user? ; circuit, user mus t modify this instru ction to fetch code mov sfrfd, a ; sfrfd(c6h) = data in mov tcon, #10 h ; tcon = 10h, tr0 = 1,go mov pcon, #01 h ; enter idle m ode (prorgamming) inc dptr inc r2 cjne r2, #0h, prog_d _32k inc r1 mov sfrah, r1 cjne r1, #80h , prog_d_32k ;******************* ******************** ******************** ****************** ; * verify 32kb apro m bank ;******************* ******************** ******************** ****************** mov r4, #03h ; error counter mov r6, #feh ; set timer for read verify, about 1.5 m s. mov r7, #ffh mov tl0, r6 mov th0, r7 mov dptr, #0h ; the start address of sample code mov r2, #0h ; target low byte address mov r1, #0h ; target high byte address mov sfrah, r1 ; sfrah, target high address mov sfrcn, #00h ; sfrcn = 00 (read rom code)
w78e58b publication release date: march 18, 2002 - 31 - revision a3 read_verify_32k: mov sfral, r2 ; sfral(c4h) = low address mov tcon, #10h ; tcon = 10h, tr0 = 1,go mov pcon, #01h inc r2 movx a, @dptr inc dptr cjne a, sfrfd, error_32k cjne r2, #0h, read_verify_32k inc r1 mov sfrah, r1 cjne r1, #80h, read _verify_32k ;****************************************************************************** ;* programming completly, software reset cpu ;****************************************************************************** mov chpenr, #87h ; chpenr = 87h mov chpenr, #59h ; chpenr = 59h mov chpcon, #83h ; chpcon = 83h, software reset. error_32k: djnz r4, update_32k ; if error occurs, repeat 3 times. . ; in - system programming fail, user's process to deal with it. . . . headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu chiu, taipei, 114, taiwan, r.o.c.

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